HSP=NOT_HIGHSSPEED, CCS=DEVICE_NOT_ATTACHED_, PR=PORT_IS_NOT_IN_THE_R, PSPD=FULL_SPEED, PFSC=ANYSPEED, PHCD=ENABLE, PTC3_0=TEST_MODE_DISABLE, PIC1_0=OFF, SUSP=PORT_NOT_IN_SUSPEND_, FPR=NO_RESUME
Port 1 status/control (device mode)
| CCS | Current connect status 0 (DEVICE_NOT_ATTACHED_): Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 1 (DEVICE_ATTACHED__A_): Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register. |
| RESERVED | Not used in device mode |
| PE | Port enable. This bit is always 1. The device port is always enabled. |
| PEC | Port enable/disable change This bit is always 0. The device port is always enabled. |
| RESERVED | Reserved |
| FPR | Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well. 0 (NO_RESUME): No resume (K-state) detected/driven on port. 1 (RESUME_DETECTED): Resume detected/driven on port. |
| SUSP | Suspend In device mode, this is a read-only status bit . 0 (PORT_NOT_IN_SUSPEND_): Port not in suspend state 1 (PORT_IN_SUSPEND_STAT): Port in suspend state |
| PR | Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register. 0 (PORT_IS_NOT_IN_THE_R): Port is not in the reset state. 1 (PORT_IS_IN_THE_RESET): Port is in the reset state. |
| HSP | High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons. 0 (NOT_HIGHSSPEED): Host/device connected to the port is not in High-speed mode. 1 (HIGHSPEED): Host/device connected to the port is in High-speed mode. |
| RESERVED | Not used in device mode. |
| RESERVED | Not used in device mode. |
| RESERVED | Reserved |
| PIC1_0 | Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins. 0 (OFF): Port indicators are off. 1 (AMBER): amber 2 (GREEN): green 3 (UNDEFINED): undefined |
| PTC3_0 | Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid. 0 (TEST_MODE_DISABLE): TEST_MODE_DISABLE 1 (J_STATE): J_STATE 2 (K_STATE): K_STATE 3 (SE0_NAK): SE0 (host)/NAK (device) 4 (PACKET): Packet 5 (FORCE_ENABLE_HS): FORCE_ENABLE_HS 6 (FORCE_ENABLE_FS): FORCE_ENABLE_FS |
| RESERVED | Not used in device mode. This bit is always 0 in device mode. |
| RESERVED | Not used in device mode. This bit is always 0 in device mode. |
| RESERVED | Not used in device mode. This bit is always 0 in device mode. |
| PHCD | PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit. 0 (ENABLE): Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled). 1 (DISABLE): Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled). |
| PFSC | Port force full speed connect 0 (ANYSPEED): Port connects at any speed. 1 (FULLSPEED): Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device. |
| RESERVED | reserved |
| PSPD | Port speed This register field indicates the speed at which the port is operating. 0 (FULL_SPEED): Full-speed 1 (INVALID_IN_DEVICE_MO): invalid in device mode 2 (HIGH_SPEED): High-speed |
| RESERVED | Reserved |